Digital integrated circuits (ICs) or chips need a reset signal for a given duration after a power supply voltage is switched on. The reset signal can place the logic circuits of the digital IC in a known initial condition. The reset signal is normally asserted at a low voltage, relative to a stabilized power supply voltage, VDD, because the IC is initially de-powered. The polarity of the reset signal may be denoted with a trailing underscore, e.g., RESET_, to indicate it is asserted low.
Generally, external power-on reset (PORST) generators may include external capacitors, resistors, buffer amplifiers, and the like. For example, a PORST generator may sense the voltage at the junction of a pull-up resistor connected to a power supply and a large external Capacitor connected to ground. The PORST generator may de-assert the reset signal when the sensed voltage crosses the threshold or trip point of the buffer amplifier, which enables the logic circuits in the IC to operate.
Further, PORST generators may not be amenable to monolithic integration on a digital IC and may raise at least two additional concerns. First, the reset duration may vary as a function of semiconductor process corners, power supply voltages, power supply rise or fall times, temperature, buffer amplifier threshold voltages, resistor tolerances, capacitor tolerances, and other factors. For example, the sense voltage that is generated in a PORST generator may have a slow rise time that is on the order of milliseconds. A slowly rising sense voltage may result in a significant device-to-device variation of the duration of the RESET signal in PORST generators without well-controlled threshold voltages because the time to cross the threshold can vary. Second, if a brief power interruption or dropout occurs, then the capacitor may not discharge enough for the reset signal to be re-asserted during and just after the power interruption. Consequently, digital circuits that rely upon the reset signal may not be placed in a known initial condition.